1. Field of the Invention
The present invention relates to a semiconductor technique for realizing, e.g., a transistor or a multilayered wiring structure having a size on the order of submicrons and, more particularly, to a semiconductor device using a self-alignment technique and a method of manufacturing the same.
2. Description of the Related Art
In recent years, a large-scale integrated (LSI) circuit formed by integrating a large number of transistors or resistors on a single chip is often used in a main part of a computer or communication equipment. To improve the performance of the LSI is the key to achieving high performance of the entire equipment. For this reason, it is important to improve the performance of a semiconductor device, e.g., a field-effect transistor which constitutes a basic element of the LSI.
In addition, a degree of integration of a memory or logic element has been increased four times every three years, and a design rule has entered a new era of submicrons. Nowadays, mass-production of 4-Mbit dRAMs having a design rule of 0.8 .mu.m and research and development of 0.3- to 0.6-.mu.m rule devices have begun.
In order to form a microelement having a deep submicron size, the following five factors are important.
(1) Lithography technique PA1 (2) Oxidizing technique (element isolating technique) PA1 (3) Diffusing technique (formation of source.drain of MOSFET, trench side wall, and emitter. base.collector of bipolar transistor) PA1 (4) Planarizing technique (metal plug formation, insulating film formation, and flattening) PA1 (5) Wiring processing technique (new material, high-selectivity etching)
The above factors will be described in detail below.